1. Field of the Invention
The present invention relates to a method for fabricating a capacitor of a semiconductor memory device, and more particularly to such a method capable of fabricating a capacitor with a very large capacitance as compared to the occupied area of a memory cell and thereby achieving improvements in the reliability and integration degree of a semiconductor memory device.
2. Description of the Prior Art
Generally, a semiconductor memory device such as a dynamic random access memory (DRAM) comprises a plurality of memory cells so as to store a large quantity of information. The memory cells of the semiconductor memory device are arranged such that each of them is connected to each corresponding one of a plurality of word lines longitudinally arranged and to each corresponding one of a plurality of bit lines laterally arranged to be orthogonal to the word lines. Each of the memory cells includes a capacitor for storing electric charges therein and a field effect transistor for opening and closing charge and discharge passages of the capacitor. Each memory cell also includes a plate electrode and a storage electrode formed to be in contact with the field effect transistor. The plate electrode and the storage electrode are mainly made of polysilicon. A dielectric film is formed between the plate electrode and the storage electrode. The dielectric film may have a single layer structure constituted by an oxide film or a nitride film or a multi-layer structure such as an oxide-nitride-oxide (ONO) structure constituted by a combination of the oxide film and the nitride film. As such a DRAM has a higher integration degree, it is difficult to ensure a sufficient storage capacitance of each capacitor. This is because each memory cell of the DRAM has an abruptly reduced occupied area as the DRAM has the higher integration degree. Such a reduction in the occupied area of a memory cell results in a reduction in the surface area of a storage electrode included in each capacitor.
Meanwhile, the capacitance C of capacitor is determined on the basis of the following equation: EQU C=(.epsilon.O.multidot..epsilon.r.multidot.A)/Tox (1)
where, so represents the permittivity of vacuum, .epsilon.r the dielectric constant, A the area of the storage electrode of the capacitor and Tox the space defined between the storage electrode and the plate electrode. In order to increase the capacitance of capacitor expressed by the equation (1), there have been proposed various methods such as a method of forming the dielectric film of capacitor by use of a dielectric material exhibiting a high dielectric constant, a method of greatly reducing the space between the storage electrode of capacitor and the plate electrode, and a method of increasing the surface area of the storage electrode of capacitor. However, these methods have problems involved in themselves.
The dielectric material, such as Ta.sub.2 O.sub.5, TiO.sub.2 or SrTiO.sub.3, exhibiting a high dielectric constant is difficult to apply to semiconductor memory devices because of its uncertain reliability and thin film characteristic such as insulation breakdown voltage. Where the space between the storage electrode and the plate electrode is reduced, the dielectric film interposed between the electrodes is reduced in thickness, so that it may be easily damaged during an operation of the memory cell. As a result, the reliability of capacitor is severely affected.
In order to increase the surface area of capacitor, there have also been proposed a method of forming a capacitor with a pin structure extending throughout a multi-layer structure of the capacitor to connect the layers with one another, a method of forming a capacitor with a cylindrical structure or a rectangular frame structure, and a method of forming a capacitor by use of a hemispherical grain polysilicon (HSG) process using polysilicon grains. Although the pin-shaped capacitor has an increased surface area by virtue of its multi-layer structure, the surface area is still small due to its reduction caused by the high integration of DRAM. As a result, the capacitance of this pin-shaped capacitor is still insufficient. The multi-layer structure rather causes a degradation in step coverage of layers subsequently formed. The cylindrical capacitor has an advantage of a low topology as compared to the pin-shaped capacitor. However, this cylindrical capacitor involves a degradation in integration degree because it occupies a large area in order to establish a sufficient capacitance in spite of its small surface area. Where the HSG process is used, an increase in surface area is obtained. In this case, however, there are problems of a difficulty in controlling the surface area and a complexity of the overall process.